Various communications protocols support a physical interface connected to a communication medium, and operate according to a protocol. For example, the PCI Express (PCIE) standard describes certain protocols for such communications. The PCIE standard is an extension of the PCI standard that uses existing PCI programming concepts. According to the PCIE standard, packets are transferred between various PCIE compatible requesters and completers of a PCIE compatible system. As is known, the PCIE standard describes a link as the collection of two ports and their interconnecting lanes and the link is a dual-simplex communications path between two components. The PCIE standard further describes a lane as a set of differential signal pairs, one pair for transmission and one pair for reception, where a by-N link is composed of N lanes. For example, a by-16 link operating at a 2.5 Giga transfers per second (GT/s) data rate represents an aggregate raw bandwidth of 40 Gigabits/second in each direction. The PCIE standard describes operations for by-1, by-2, by-4, by-8, by-12, by-16, and by-32 links.
The PCIE standard describes a symbol as a 10-bit quantity using 8 bit (b)/10b encoding (8 bits encoded as 10 bits), and an 8-bit quantity using 128b/130b encoding (2 bits of Sync Header and 128 bits of payload). The PCIE standard also describes the symbol time as the period of time to place a symbol on a lane (10 times a unit interval when using 8b/10b encoding, and 8 times a unit interval when using 128b/130b encoding). The PCIE standard further describes the unit interval as the value measured by averaging the time interval per bit, over a time interval long enough to make all intentional frequency modulation of the source clock negligible.
Once a PCIE compatible system initializes each link, the link operates at one of the supported data rates. The PCIE 1.0a standard specifies an effective data rate of 2.5 Gigabits per second, per lane, per direction, of raw bandwidth. The PCIE 2.0 standard specifies an effective data rate of 5.0 Gigabits per second, per lane, per direction, of raw bandwidth. The PCIE 3.0 standard specifies an effective data rate of 8.0 Gigabits per second, per lane, per direction, of raw bandwidth. Also, the future PCIE 4.0 standard is expected to specify an effective data rate of 16.0 Gigabits per second, per lane, per direction, of raw bandwidth. Future versions of the PCIE standard will likely continue to increase the specified data rate. For example, historically the PCIE standard has doubled the PCIE bandwidth for each major revision (generally every 3-4 years).
As communication standards such as the PCIE standard continue to specify increasing data rates, the design of the associated communication controllers will become increasingly difficult.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.